Job type: Vollzeit, Festanstellung

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We are growing! We are looking for a Staff Engineer Digital Verification for our site in Graz. You have a pioneering spirit, a passion for technology and would like to shape the future of mobile applications? Then join our high-performance team and apply now!
In this role you will be part of an international team working on the leading-edge of technology to find solutions for our next generation MEMS microphones. As a Digital Verification Engineer you will be responsible for the digital pre-silicon verification of our SoCs (System on Chip).

In this job the main duties and responsibilities include:
  • Digital verificationof mixed-signal designs on blockand system levelbased on functional and formal verification
  • Interpretationof product requirementsto derive verification conceptand product verification specification
  • Implementation ofstate of the art random-constraint testbenches
  • Writingof assertionsto proof designwith formal methods
  • Working in close cooperationwith verification engineers, designers, system architects, laband test engineersin a multi-site setting
During atraining phasewe will support preparing you for your tasks and responsibilities. With regularfeedbackdiscussions and planning of yourprofessional and personal developmentwe want to ensure your success in this position.

As a true team player, you treat your colleagues with respect and trust. You can convince with an abilityto learn quicklyand understandcomplexinteractionssuch as algorithms. You are a goodnetworker, you can quickly establishsuccessfulcooperation’sand you put the team’s results above your own interests. You have strongcommunicationskillsand a strong focus on quality.

You are best equipped for this job if you have:
  • A university / university of applied sciences degree (Master)in Electrical Engineering, Computer Scienceor comparable
  • Ideally 3 year+ practical experiencein the field of digital functional verification
  • Good programming skillsin coding in System Verilog and System Verilog Assertions
  • Ability to interpret RTL and Gatelevel code
  • Experience with UVM methodologyis highly desired
  • Experience in at least one scripting languages like Python or Perl
  • Ideally first experience as lead engineerresponsible for planning, tracking and reporting of the team success as main interface towards project management
  • Fluent Englishskills with Germanskills as a plus
This position is subject to the collective agreement for workers and employees in the electrical and electronics industry, employment group G-H ( A higher payment is negotiable depending on your expertise and skills.

Almost 4.600 people work at five different sites in Austria.

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